CH5008中文資料ETC數(shù)據(jù)手冊PDF規(guī)格書

FEATURES

Dual SDH STM-1 serial LVPCEL interfaces

Integrated two-channel CDR macros to interface directly with an

optical module

Fully compliant with ITU-T specifications for Jitter Tolerance,

Transfer and Generation

Regenerator and multiplexer section termination

High order processing for AU-4 pointer interpretation/generation

and POH termination

Full access to SOH through a serial interface.

Integrated MSP processing to support 1+1, 1:n protection

Byte-wide 19.44MHz Extension Telecom Bus

Aligns SDH tributary TU3/TU12 for every TUG3 within 8 STM-1 or bypass

Integrated 21 channels E1 mapper for asynchronous mapping and de-mapping to/from a STM-1 with re-timing

support on eight channels.

The output jitter of 2M data (either mapping jitter or combined jitter) is compliant with G.783 (2000/10)

Supports 1+1 low order path protection.

Build-in PRBS test function

6x6 non-blocking switching for high and low order cross connection

1.8V/3.3V supply, 3.3V CMOS and LVPECL I/O

IEEE 1149.1 boundary scan

Operating industrial temperature range: -40℃ ~ 85℃

Maximum power consumption less than 3.6 W

TEBGA421 package

APPLICATIONS

SDH Add/Drop Multiplexers

SDH Terminal Multiplexers

Multi-service Transport Platform (MSTP)

Customer Premises Equipment (CPE)