CP1121A中文資料ETC數(shù)據(jù)手冊PDF規(guī)格書

FEATURES

Supports up to four ports of full-duplex10/100 Mbit/s Ethernet or a single port of full-duplex 1000 Mbit/s

Ethernet with standards-compliant flow control supported:

10/100 Mbit/s Ethernet interface supports SMII and SS-SMII

1000 Mbit/s Ethernet interface supports GMII

Ethernet Management interface (MDIO) for control and configuration of external connected PHYs

Provides IEEE 802.3 Management Statistics (RMON)

Supports multiple virtual concatenation groups from one Ethernet port based on VLAN tag identification

Supports multiple virtual concatenation groups to one Ethernet port based on the user’s configuration

Supports up to 16 virtual concatenation groups

Supports up to four priority queues, enabling time-sensitive data to have access to the network with

minimal delay

Provides RED algorithm for buffer management

Provides per-priority scheduling using Round Robin mechanism

Supports the following encapsulation/decapsulation protocols on a per port basis:

ITU-T G.7041, Generic Framing Procedure (GFP)

HDLC-like Framing, including the following protocols:

ITU-T X.86/X.85, Link Access Procedure SDH (LAPS)

RFC1662, Point-to-Point Protocol (PPP)

RFC3518, PPP Bridging Control Protocol (BCP)

Supports the following SDH mapping formats:

C-12/VC-12/TU-12/TUG-2/TUG-3/VC-4/AU-4/STM-1

C-3/VC-3/TU-3/TUG-3/VC-4/AU-4/STM-1

C-4/VC-4/AU-4/STM-1

Supports selection of VC-4, VC-3 or VC-12 virtual concatenation on a per virtual concatenation group

basis

Supports hitless Link Capacity Adjustment Scheme (LCAS) (ITU-T G.7042)

Supports up to 240ms (VC-12)/254ms (VC-3) of differential delay

Supports TU-12/TU-3 pointer interpretation

Supports VC-12, VC-3 and VC-4 POH generation and termination

Full access VC-12, VC-3 and VC-4 POH through external serial interface

Provides byte-wide 19.44MHz Telecom Bus interface

Controlled High-Z output on Output Telecom Bus

Provides three bus timing modes for Output Telecom Bus

Supports per-port Ethernet side and SDH system side loopbacks for system level diagnostics

Provides 16-bit Intel/Motorola microprocessor interface

Provides an IEEE 1149.1 compliant JTAG test port for boundary scan

Operating Industrial temperature range: -40℃ ~ 85℃

Low power 1.8V core with 3.3V LVTTL I/O, LVPECL I/O and 2.5V SSTL_2 digital I/O

The maximum power consumption is 2.1W

27x27mm PBGA 352 package