CY7C025V中文資料賽普拉斯數(shù)據(jù)手冊PDF規(guī)格書

Features

? True dual-ported memory cells which allow simultaneous access of the same memory location

? 4/8/16K x 16 organization (CY7C024V/025V/026V)

? 4/8K x 18 organization (CY7C0241V/0251V)

? 16K x 18 organization (CY7C036V)

? 0.35-micron CMOS for optimum speed/power

? High-speed access: 15[1]/20/25 ns

? Low operating power

— Active: ICC = 115 mA (typical)

— Standby: ISB3 = 10 μA (typical)

? Fully asynchronous operation

? Automatic power-down

? Expandable data bus to 32/36 bits or more using Master/Slave chip select when using more than one device

? On-chip arbitration logic

? Semaphores included to permit software handshaking between ports

? INT flag for port-to-port communication

? Separate upper-byte and lower-byte control

? Pin select for Master or Slave

? Commercial and industrial temperature ranges

? Available in 100-pin TQFP

? Pin-compatible and functionally equivalent to IDT70V24, 70V25, and 7V0261.