CY7C1212F中文資料賽普拉斯數(shù)據(jù)手冊(cè)PDF規(guī)格書

Functional Description[1]

The CY7C1212F SRAM integrates 65,536 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation.

Features

? Registered inputs and outputs for pipelined operation

? 64K × 18 common I/O architecture

? 3.3V core power supply

? 3.3V I/O operation

? Fast clock-to-output times

— 3.5 ns (for 166-MHz device)

— 4.0 ns (for 133-MHz device)

? Provide high-performance 3-1-1-1 access rate

? User-selectable burst counter supporting Intel? Pentium? interleaved or linear burst sequences

? Separate processor and controller address strobes

? Synchronous self-timed writes

? Asynchronous output enable

? Offered in JEDEC-standard 100-pin TQFP package

? “ZZ” Sleep Mode Option