CY7C1318AV18中文資料賽普拉斯數(shù)據(jù)手冊PDF規(guī)格書

Functional Description

The CY7C1316AV18/CY7C1318AV18/CY7C1320AV18 are 1.8V Synchronous Pipelined SRAM equipped with DDR-II architecture. The DDR-II consists of an SRAM core with advanced synchronous peripheral circuitry and a 1-bit burst counter.

Features

? 18-Mb density (2M x 8, 1M x 18, 512K x 36)

? 250-MHz clock for high bandwidth

? 2-Word burst for reducing address bus frequency

? Double Data Rate (DDR) interfaces (data transferred at 500 MHz) @ 250 MHz

? Two input clocks (K and K) for precise DDR timing

— SRAM uses rising edges only

? Two output clocks (C and C) account for clock skew and flight time mismatching

? Echo clocks (CQ and CQ) simplify data capture in high-speed systems

? Synchronous internally self-timed writes

? 1.8V core power supply with HSTL inputs and outputs

? Variable drive HSTL output buffers

? Expanded HSTL output voltage (1.4V–VDD)

? 13 x 15 x 1.4 mm 1.0-mm pitch fBGA package, 165 ball (11x15 matrix)

? JTAG 1149.1 compatible test access port

? Delay Lock Loop (DLL) for accurate data placement