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CY7C1320CV18-200BZI中文資料賽普拉斯數(shù)據(jù)手冊PDF規(guī)格書

CY7C1320CV18-200BZI
廠商型號

CY7C1320CV18-200BZI

功能描述

18-Mbit DDR-II SRAM 2-Word Burst Architecture

文件大小

662.26 Kbytes

頁面數(shù)量

29

生產(chǎn)廠商 CypressSemiconductor
企業(yè)簡稱

Cypress賽普拉斯

中文名稱

賽普拉斯半導(dǎo)體公司官網(wǎng)

原廠標(biāo)識
數(shù)據(jù)手冊

下載地址一下載地址二到原廠下載

更新時間

2025-1-4 20:00:00

CY7C1320CV18-200BZI規(guī)格書詳情

Functional Description

The CY7C1316CV18, CY7C1916CV18, CY7C1318CV18, and CY7C1320CV18 are 1.8V Synchronous Pipelined SRAMs equipped with DDR-II architecture. The DDR-II consists of an SRAM core with advanced synchronous peripheral circuitry and a one-bit burst counter. Addresses for read and write are latched on alternate rising edges of the input (K) clock.

Features

■18-Mbit density (2M x 8, 2M x 9, 1M x 18, 512K x 36)

■267 MHz clock for high bandwidth

■2-word burst for reducing address bus frequency

■Double Data Rate (DDR) interfaces (data transferred at 534 MHz) at 267 MHz

■Synchronous internally self-timed writes

■DDR-II operates with 1.5 cycle read latency when the DLL is enabled

■Operates similar to a DDR-I device with 1 cycle read latency in DLL off mode

■1.8V core power supply with HSTL inputs and outputs

■Variable drive HSTL output buffers

■Expanded HSTL output voltage (1.4V–VDD)

■Available in 165-Ball FBGA package (13 x 15 x 1.4 mm)

■Offered in both Pb-free and non Pb-free packages

■JTAG 1149.1 compatible test access port

■Delay Lock Loop (DLL) for accurate data placement

供應(yīng)商 型號 品牌 批號 封裝 庫存 備注 價格
CYP
23+
NA/
2811
優(yōu)勢代理渠道,原裝正品,可全系列訂貨開增值稅票
詢價
CYPRESS
23+
165FBGA
4568
原廠原裝正品現(xiàn)貨,代理渠道,支持訂貨!!!
詢價
Cypress
23+
165-FBGA
65600
詢價
CYPRESS
22+23+
165FBGA
23249
絕對原裝正品全新進(jìn)口深圳現(xiàn)貨
詢價
CYP
BGA
68900
原包原標(biāo)簽100%進(jìn)口原裝常備現(xiàn)貨!
詢價
Cypress
23+
165-FBGA(13x15)
36430
專業(yè)分銷產(chǎn)品!原裝正品!價格優(yōu)勢!
詢價
Cypress
21+
25000
原廠原包 深圳現(xiàn)貨 主打品牌 假一賠百 可開票!
詢價
Cypress
24+
BGA165
85
詢價
Cypress
21+
165FBGA (13x15)
13880
公司只售原裝,支持實單
詢價
CYP
22+
BGA
62100
鄭重承諾只做原裝進(jìn)口現(xiàn)貨
詢價