CY7C1327B中文資料賽普拉斯數(shù)據(jù)手冊PDF規(guī)格書

Functional Description

The CY7C1327B is a 3.3V, 256K by 18 synchronous-pipelined cache SRAM designed to support zero wait state secondary cache with minimal glue logic.

Features

? Supports 100-MHz bus for Pentium? and PowerPC? operations with zero wait states

? Fully registered inputs and outputs for pipelined operation

? 256K by 18 common I/O architecture

? 3.3V core power supply

? 2.5V / 3.3V I/O operation

? Fast clock-to-output times

— 3.5 ns (for 166-MHz device)

— 4.0 ns (for 133-MHz device)

— 5.5 ns (for 100-MHz device)

? User-selectable burst counter supporting Intel? Pentium interleaved or linear burst sequences

? Separate processor and controller address strobes

? Synchronous self-timed writes

? Asynchronous Output Enable

? JEDEC-standard 100 TQFP pinout

? “ZZ” Sleep Mode option and Stop Clock option