CY7C1327G-100BGC中文資料賽普拉斯數(shù)據(jù)手冊PDF規(guī)格書

Features

? Registered inputs and outputs for pipelined operation

? 256K ×18 common I/O architecture

? 3.3V core power supply

? 3.3V / 2.5V I/O operation

? Fast clock-to-output times

— 2.6 ns (for 250-MHz device)

— 2.6 ns (for 225-MHz device)

— 2.8 ns (for 200-MHz device)

— 3.5 ns (for 166-MHz device)

— 4.0 ns (for 133-MHz device)

— 4.5 ns (for 100-MHz device)

? Provide high-performance 3-1-1-1 access rate

? User-selectable burst counter supporting Intel?

Pentium? interleaved or linear burst sequences

? Separate processor and controller address strobes

? Synchronous self-timed writes

? Asynchronous output enable

? Lead-Free 100-pin TQFP and 119 Ball BGA packages.

? “ZZ” Sleep Mode Option