CY7C1339B-100AC中文資料賽普拉斯數(shù)據(jù)手冊PDF規(guī)格書

Functional Description

The CY7C1339B is a 3.3V, 128K by 32 synchronous-pipelined cache SRAM designed to support zero wait state secondary cache with minimal glue logic.

The CY7C1339B I/O pins can operate at either the 2.5V or the 3.3V level; the I/O pins are 3.3V-tolerant when VDDQ = 2.5V.

All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise is 3.5 ns (166-MHz device).

The CY7C1339B supports either the interleaved burst sequence used by the Intel Pentium processor or a linear burst sequence used by processors such as the PowerPC.

Features

? Supports 100-MHz bus for Pentium? and PowerPC? operations with zero wait states

? Fully registered inputs and outputs for pipelined operation

? 128K × 32 common I/O architecture

? 3.3V core power supply

? 2.5V / 3.3V I/O operation

? Fast clock-to-output times

— 3.5 ns (for 166-MHz device)

— 4.0 ns (for 133-MHz device)

— 5.5 ns (for 100-MHz device)

? User-selectable burst counter supporting Intel? Pentium interleaved or linear burst sequences

? Separate processor and controller address strobes

? Synchronous self-timed writes

? Asynchronous output enable

? Offered in JEDEC-standard 100-pin TQFP and 119-ball BGA packages

? “ZZ” Sleep Mode and Stop Clock options