CY7C1340F中文資料賽普拉斯數(shù)據(jù)手冊(cè)PDF規(guī)格書

Functional Description[1]

The CY7C1340F SRAM integrates 131,072 x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK).

Features

? Registered inputs and outputs for pipelined operation

? Optimal for performance (Double-Cycle deselect)

— Depth expansion without wait state

? 128K × 32-bit common I/O architecture

? 3.3V –5 and +10 core power supply (VDD)

? 3.3V / 2.5V I/O supply (VDDQ)

? Fast clock-to-output times

— 2.6 ns (for 250-MHz device)

— 2.6 ns (for 225-MHz device)

— 2.8 ns (for 200-MHz device)

— 3.5 ns (for 166-MHz device)

— 4.0 ns (for 133-MHz device)

— 4.5 ns (for 100-MHz device)

? Provide high-performance 3-1-1-1 access rate

? User-selectable burst counter supporting Intel? Pentium? interleaved or linear burst sequences

? Separate processor and controller address strobes

? Synchronous self-timed writes

? Asynchronous Output Enable

? JEDEC-standard 100-pin TQFP package and pinout

? “ZZ” Sleep Mode option