CY7C1347D-250BGC中文資料賽普拉斯數(shù)據(jù)手冊PDF規(guī)格書

Functional Description

This Cypress Synchronous Burst SRAM employs high-speed, low-power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high-valued resistors.

The CY7C1347D SRAM integrate 131,072 x 36 SRAM cells with advanced synchronous peripheral circuitry and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input (CLK).

Features

? Fast access times: 2.5 and 3.5 ns

? Fast clock speed: 250, 225, 200, and 166 MHz

? 1.5-ns set-up time and 0.5-ns hold time

? Fast OE access times: 2.5 ns and 3.5 ns

? Optimal for depth expansion (one cycle chip deselect to eliminate bus contention)

? 3.3V –5 and +10 power supply

? 3.3V or 2.5V I/O supply

? 5V tolerant inputs except I/Os

? Clamp diodes to VSS at all inputs and outputs

? Common data inputs and data outputs

? Byte Write Enable and Global Write control

? Three chip enables for depth expansion and address pipeline

? Address, data, and control registers

? Internally self-timed Write Cycle

? Burst control pins (interleaved or linear burst sequence)

? Automatic power-down for portable applications

? JTAG boundary scan

? JEDEC standard pinout

? Low profile 119-lead, 14-mm x 22-mm BGA (Ball Grid Array) and 100-pin TQFP packages