CY7C1347F-200BZC中文資料賽普拉斯數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

Functional Description[1]

The CY7C1347F is a 3.3V, 128K by 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic.

CY7C1347F I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when VDDQ = 2.5V.

All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise is 2.6 ns (250-MHz device)

CY7C1347F supports either the interleaved burst sequence used by the Intel Pentium processor or a linear burst sequence used by processors such as the PowerPC?.

Features

? Fully registered inputs and outputs for pipelined operation

? 128K by 36 common I/O architecture

? 3.3V core power supply

? 2.5V/3.3V I/O operation

? Fast clock-to-output times

— 2.6 ns (for 250-MHz device)

— 2.6 ns (for 225-MHz device)

— 2.8 ns (for 200-MHz device)

— 3.5 ns (for 166-MHz device)

— 4.0 ns (for 133-MHz device)

? User-selectable burst counter supporting Intel? Pentium? interleaved or linear burst sequences

? Separate processor and controller address strobes

? Synchronous self-timed writes

? Asynchronous output enable

? JEDEC-standard 100-pin TQFP, 119-pin BGA and 165-pin fBGA packages

? “ZZ” Sleep Mode option and Stop Clock option

? Available in Industrial and Commercial temperature ranges