CY7C1350G-100AXI中文資料賽普拉斯數(shù)據(jù)手冊(cè)PDF規(guī)格書

Functional Description[1]

The CY7C1350G is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350G is equipped with the advanced No Bus Latency? (NoBL?) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of the SRAM, especially in systems that require frequent Write/Read transitions.

Features

? Pin compatible and functionally equivalent to ZBT? devices

? Internally self-timed output buffer control to eliminate the need to use OE

? Byte Write capability

? 128K x 36 common I/O architecture

? 3.3V power supply (VDD)

? 2.5V/3.3V I/O power supply (VDDQ)

? Fast clock-to-output times — 2.6 ns (for 250-MHz device)

? Clock Enable (CEN) pin to suspend operation

? Synchronous self-timed writes

? Asynchronous output enable (OE)

? Available in lead-free 100-Pin TQFP package, lead-free and non-lead-free 119-Ball BGA package

? Burst Capability—linear or interleaved burst order

? “ZZ” Sleep mode option