CY7C1355A中文資料賽普拉斯數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

Functional Description

The CY7C1355A and CY7C1357A SRAMs are designed to eliminate dead cycles when transitions from READ to WRITE or vice versa. These SRAMs are optimized for 100 percent bus utilization and achieves Zero Bus Latency (ZBL). They integrate 262,144 × 36 and 524,288 × 18 SRAM cells, respectively, with advanced synchronous peripheral circuitry and a 2-bit counter for internal burst operation. These employ high-speed, low power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of Six transistors.

Features

? Zero Bus Latency, no dead cycles between write and read cycles

? Fast access times: 2.5 ns, 3.0 ns, and 3.5 ns

? Fast clock speed: 133, 117, and 100 MHz

? Fast OE access time: 6.5, 7.0, and 7.5ns

? Internally synchronized registered outputs eliminate the need to control OE

? 3.3V –5 and +5 power supply

? 3.3V or 2.5V I/O supply

? Single WEN (READ/WRITE) control pin

? Positive clock-edge triggered, address, data, and control signal registers for fully pipelined applications

? Interleaved or linear four-word burst capability

? Individual byte write (BWa–BWd) control (may be tied LOW)

? CEN pin to enable clock and suspend operations

? Three chip enables for simple depth expansion

? Automatic Power-down feature available using ZZ mode or CE deselect.

? JTAG boundary scan (except CY7C1357A)

? Low-profile 119-bump, 14-mm × 22-mm BGA (Ball Grid Array) for CY7C1355A, and 100-pin TQFP packages for both devices