CY7C136-55JC中文資料賽普拉斯數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

Functional Description

The CY7C132, CY7C136, CY7C136A, CY7C142, and CY7C146 are high speed CMOS 2K x 8 dual-port static RAMs. Two ports are provided to permit independent access to any location in memory. The CY7C132, CY7C136, and CY7C136A can be used as either a standalone 8-bit dual-port static RAM or as a MASTER dual-port RAM, in conjunction with the CY7C142/CY7C146 SLAVE dual-port device. They are used in systems that require 16-bit or greater word widths. This is the solution to applications that require shared or buffered data, such as cache memory for DSP, bit-slice, or multiprocessor designs.

Features

■ True dual-ported memory cells that enable simultaneous reads of the same memory location

■ 2K x 8 organization

■ 0.65 micron CMOS for optimum speed and power

■ High speed access: 15 ns

■ Low operating power: ICC = 110 mA (maximum)

■ Fully asynchronous operation

■ Automatic power down

■ Master CY7C132/CY7C136/CY7C136A[1] easily expands data bus width to 16 or more bits using slave CY7C142/CY7C146

■ BUSY output flag on CY7C132/CY7C136/CY7C136A; BUSY input on CY7C142/CY7C146

■ INT flag for port to port communication (52-Pin PLCC/PQFP versions)

■ CY7C136, CY7C136A, and CY7C146 available in 52-pin PLCC and 52-pin PQFP packages

■ Pb-free packages available