CY7C1361A-100AJI中文資料賽普拉斯數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

Functional Description

The Cypress Synchronous Burst SRAM family employs high-speed, low-power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high-valued resistors.

Features

? Fast access times: 6.0, 6.5, 7.0, and 8.0ns

? Fast clock speed: 150, 133, 117, and 100MHz

? Fast OE access times: 3.5 ns and 4.0 ns

? Optimal for depth expansion (one cycle chip deselect to eliminate bus contention)

? 3.3V –5 and +10 power supply

? 3.3V or 2.5V I/O supply

? 5V tolerant inputs except I/Os

? Clamp diodes to VSS at all inputs and outputs

? Common data inputs and data outputs

? Byte Write Enable and Global Write control

? Multiple chip enables for depth expansion: A package version and two chip enables for BG and AJ package versions

? Address pipeline capability

? Address, data, and control registers

? Internally self-timed Write cycle

? Burst control pins (interleaved or linear burst sequence)

? Automatic power-down feature available using ZZ mode or CE deselect.

? JTAG boundary scan for BG and AJ package version

? Low-profile 119-bump 14-mm × 22-mm PBGA (Ball Grid Array) and 100-pin TQFP packages