CY7C1381D-100AXI中文資料賽普拉斯數(shù)據(jù)手冊PDF規(guī)格書

Functional Description [1]

The CY7C1381D/CY7C1383D/CY7C1381F/CY7C1383F is a 3.3V, 512K x 36 and 1M x 18 synchronous flow through SRAMs, designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133 MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access.

Features

? Supports 133 MHz bus operations

? 512K × 36 and 1M × 18 common IO

? 3.3V core power supply (VDD)

? 2.5V or 3.3V IO supply (VDDQ)

? Fast clock-to-output time

— 6.5 ns (133 MHz version)

? Provides high performance 2-1-1-1 access rate

? User selectable burst counter supporting Intel? Pentium? interleaved or linear burst sequences

? Separate processor and controller address strobes

? Synchronous self-timed write

? Asynchronous output enable

? CY7C1381D/CY7C1383D available in JEDEC-standard

Pb-free 100-pin TQFP, Pb-free and non Pb-free 165-ball

FBGA package. CY7C1381F/CY7C1383F available in

Pb-free and non Pb-free 119-ball BGA package

? IEEE 1149.1 JTAG-Compatible Boundary Scan

? ZZ sleep mode option