CY7C1440AV33-200AXC中文資料賽普拉斯數(shù)據(jù)手冊(cè)PDF規(guī)格書

Functional Description[1]

The CY7C1440AV33/CY7C1442AV33/CY7C1446AV33 SRAM integrates 1M x 36/2M x 18 and 512K x 72 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BWX and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin.

Features

? Supports bus operation up to 250 MHz

? Available speed grades are 250, 200 and 167 MHz

? Registered inputs and outputs for pipelined operation

? 3.3V core power supply

? 2.5V/3.3V I/O power supply

? Fast clock-to-output times

— 2.6 ns (for 250-MHz device)

? Provide high-performance 3-1-1-1 access rate

? User-selectable burst counter supporting Intel?

Pentium? interleaved or linear burst sequences

? Separate processor and controller address strobes

? Synchronous self-timed writes

? Asynchronous output enable

? Single Cycle Chip Deselect

? CY7C1440AV33, CY7C1442AV33 available in lead-free

100-pin TQFP package, lead-free and non-lead-free

165-ball FBGA package. CY7C1446AV33 available in

lead-free and non-lead-free 209-ball FBGA package

? Also available in lead-free packages

? IEEE 1149.1 JTAG-Compatible Boundary Scan

? “ZZ” Sleep Mode Option