CY7C1464AV33-200中文資料賽普拉斯數(shù)據(jù)手冊(cè)PDF規(guī)格書

Functional Description

The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 are 3.3V, 1M x 36/2M x 18/512K x72 Synchronous pipelined burst SRAMs with No Bus Latency? (NoBL?) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 are equipped with the advanced (NoBL) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data in systems that require frequent Write/Read transitions. The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 are pin compatible and functionally equivalent to ZBT devices.

Features

? Pin-compatible and functionally equivalent to ZBT?

? Supports 250-MHz bus operations with zero wait states

— Available speed grades are 250, 200 and 167 MHz

? Internally self-timed output buffer control to eliminate the need to use asynchronous OE

? Fully registered (inputs and outputs) for pipelined operation

? Byte Write capability

? 3.3V power supply

? 3.3V/2.5V I/O power supply

? Fast clock-to-output times

— 2.6 ns (for 250-MHz device)

? Clock Enable (CEN) pin to suspend operation

? Synchronous self-timed writes

? CY7C1460AV33, CY7C1462AV33 available in

JEDEC-standard lead-free 100-pin TQFP, lead-free and

non-lead-free 165-ball FBGA package. CY7C1464AV33

available in lead-free and non-lead-free 209-ball FBGA

package

? IEEE 1149.1 JTAG-Compatible Boundary Scan

? Burst capability—linear or interleaved burst order

? “ZZ” Sleep Mode option and Stop Clock option