CY7C1480V33-200BZC中文資料賽普拉斯數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

Functional Description[1]

The CY7C1480V33/CY7C1482V33/CY7C1486V33 SRAM integrates 2M x 36/4M x 18/1M × 72 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK).

Features

? Supports bus operation up to 250 MHz

? Available speed grades are 250, 200 and 167 MHz

? Registered inputs and outputs for pipelined operation

? 3.3V core power supply

? 2.5V/3.3V I/O operation

? Fast clock-to-output times

— 3.0 ns (for 250-MHz device)

? Provide high-performance 3-1-1-1 access rate

? User-selectable burst counter supporting Intel? Pentium? interleaved or linear burst sequences

? Separate processor and controller address strobes

? Synchronous self-timed writes

? Asynchronous output enable

? Single Cycle Chip Deselect

? CY7C1480V33, CY7C1482V33 available in

JEDEC-standard lead-free 100-pin TQFP, lead-free and

non-lead-free 165-ball FBGA package. CY7C1486V33

available in lead-free and non-lead-free 209 ball FBGA

package

? IEEE 1149.1 JTAG-Compatible Boundary Scan

? “ZZ” Sleep Mode Option