CY7C1486BV25中文資料賽普拉斯數(shù)據(jù)手冊PDF規(guī)格書

Functional Description

The CY7C1480BV25/CY7C1482BV25/CY7C1486BV25[1] SRAM integrates 2M x 36/4M x 18/1M × 72 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BWX, and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin.

Features

■ Supports bus operation up to 250 MHz

■ Available speed grades are 250, 200, and 167 MHz

■ Registered inputs and outputs for pipelined operation

■ 2.5V core power supply

■ 2.5V IO operation

■ Fast clock-to-output time

? 3.0 ns (for 250 MHz device)

■ Provide high performance 3-1-1-1 access rate

■ User selectable burst counter supporting Intel? Pentium? interleaved or linear burst sequences

■ Separate processor and controller address strobes

■ Synchronous self timed writes

■ Asynchronous output enable

■ Single cycle chip deselect

■ CY7C1480BV25, CY7C1482BV25 available in

JEDEC-standard Pb-free 100-pin TQFP, Pb-free and

non-Pb-free 165-ball FBGA package. CY7C1486BV25

available in Pb-free and non-Pb-free 209-ball FBGA package

■ IEEE 1149.1 JTAG-Compatible Boundary Scan

■ “ZZ” Sleep Mode option