CY7C4271-35AC中文資料賽普拉斯數(shù)據(jù)手冊PDF規(guī)格書

Functional Description

The CY7C4261/71 are high-speed, low-power FIFO memories with clocked read and write interfaces. All are nine bits wide. The CY7C4261/71 are pin-compatible to the CY7C42X1 Synchronous FIFO family. The CY7C4261/71 can be cascaded to increase FIFO width. Programmable features include Almost Full/Almost Empty flags. These FIFOs provide solutions for a wide variety of data buffering needs, including high-speed data acquisition, multiprocessor interfaces, and communications buffering.

Features

? High-speed, low-power, first-in first-out (FIFO) memories

? 16K × 9 (CY7C4261)

? 32K × 9 (CY7C4271)

? 0.5-micron CMOS for optimum speed/power

? High-speed 100-MHz operation (10-ns read/write cycle times)

? Low power — ICC = 35 mA

? Fully asynchronous and simultaneous read and write operation

? Empty, Full, Half Full, and programmable Almost Empty and Almost Full status flags

? TTL-compatible

? Output Enable (OE) pins

? Independent read and write enable pins

? Center power and ground pins for reduced noise

? Supports free-running 50 duty cycle clock inputs

? Width-Expansion Capability

? Military temp SMD Offering – CY7C4271-15LMB

? 32-pin PLCC/LCC and 32-pin TQFP

? Pin-compatible density upgrade to CY7C42X1 family

? Pin-compatible density upgrade to IDT72201/11/21/31/41/51

? Pb-Free Packages Available