CY7C4821-25AC中文資料賽普拉斯數(shù)據(jù)手冊(cè)PDF規(guī)格書

Functional Description

The CY7C48X1 are Double high-speed, low-power, first-in first-out (FIFO) memories with clocked read and write interfaces. All are 9 bits wide and operate as two separate FIFOs. The CY7C48X1 are pin-compatible to IDT728X1. Programmable features include Almost Full/Almost Empty flags. These FIFOs provide solutions for a wide variety of data buffering needs, including high-speed data acquisition, multiprocessor interfaces, and communications buffering.

Features

? Double high speed, low power, first-in first-out (FIFO) memories

? Double 256 x 9 (CY7C4801)

? Double 512 x 9 (CY7C4811)

? Double 1K x 9 (CY7C4821)

? Double 2K x 9 (CY7C4831)

? Double 4K x 9 (CY7C4841)

? Double 8K x 9 (CY7C4851)

? Functionally equivalent to two CY7C4201/4211/4221/ 4231/4241/4251 FIFOs in a single package

? 0.65 micron CMOS for optimum speed/power

? High-speed 100-MHz operation (10 ns read/write cycle times)

? Offers optimal combination of large capacity, high speed, design flexibility, and small footprint

? Fully asynchronous and simultaneous read and write operation

? Four status flags per device: Empty, Full, and programmable Almost Empty/Almost Full

? Low power — ICC1= 60mA

? Output Enable (OEA/OEB) pins

? Depth Expansion Capability

? Width Expansion Capability

? Space-saving 64-pin TQFP

? Pin compatible and functionally equivalent to IDT72801, 72811, 72821, 72831, 72841,72851