CY8C20334集成電路（IC）的微控制器規(guī)格書PDF中文資料

PSoC Functional Overview

The PSoC family consists of many Programmable System-on-Chips with On-Chip Controller devices. These devices are designed to replace multiple traditional MCU based system components with one low cost single chip programmable component. A PSoC device includes configurable analog and digital blocks and programmable interconnect. This architecture enables the user to create customized peripheral configurations to match the requirements of each individual application. Additionally, a fast CPU, flash program memory, SRAM data memory, and configurable I/O are included in a range of convenient pinouts.

Features

■ Low power CapSense? block

? Configurable capacitive sensing elements

? Supports combination of CapSense buttons, sliders, touchpads, and proximity sensors

■ Powerful Harvard-architecture processor

? M8C processor speeds running up to 12 MHz

? Low power at high speed

? Operating voltage: 2.4 V to 5.25 V

? Industrial temperature range: –40 °C to +85 °C

■ Flexible on-chip memory

? 8 KB flash program storage 50,000 erase/write cycles

? 512-Bytes SRAM data storage

? Partial flash updates

? Flexible protection modes

? Interrupt controller

? In-system serial programming (ISSP)

■ Complete development tools

? Free development tool (PSoC Designer?)

? Full-featured, in-circuit emulator, and programmer

? Full-speed emulation

? Complex breakpoint structure

? 128 KB trace memory

■ Precision, programmable clocking

? Internal ±5.0 6- / 12-MHz main oscillator

? Internal low speed oscillator at 32 kHz for watchdog and sleep

■ Programmable pin configurations

? Pull-up, high Z, open-drain, and CMOS drive modes on all GPIOs

? Up to 28 analog inputs on all GPIOs

? Configurable inputs on all GPIOs

? 20-mA sink current on all GPIOs

? Selectable, regulated digital I/O on port 1

? 3.0 V, 20 mA total port 1 source current

? 5 mA strong drive mode on port 1 versatile analog mux

? Common internal analog bus

? Simultaneous connection of I/O combinations

? Comparator noise immunity

? Low-dropout voltage regulator for the analog array

■ Additional system resources

? Configurable communication speeds

? I2C: selectable to 50 kHz, 100 kHz, or 400 kHz

? SPI: configurable between 46.9 kHz and 3 MHz

? I2C slave

? SPI master and SPI slave

? Watchdog and sleep timers

? Internal voltage reference

? Integrated supervisory circuit