General description

PSoC? 6 MCU is a high-performance, ultra-low-power and secured MCU platform, purpose-built for IoT

applications. The CY8C61x6/7 product line, based on the PSoC? 6 MCU platform, is a combination of a

high-performance microcontroller with low-power flash technology, digital programmable logic,

high-performance analog-to-digital conversion and standard communication and timing peripherals.

Features

? 32-bit dual CPU subsystem

Note: In PSoC? 61 the Cortex? M0+ is reserved for system functions, and is not available for applications.

- 150-MHz Arm? Cortex?-M4F (CM4) CPU with single-cycle multiply, floating point, and memory protection unit

(MPU)

- 100-MHz Cortex?-M0+ (CM0+) CPU with single-cycle multiply and MPU

- Core logic operation at either 1.1 V or 0.9 V, depending on the part selected. See Ordering information.

- Active CPU current slope with 1.1-V core operation

? Cortex?-M4: 40 μA/MHz

? Cortex?-M0+: 20 μA/MHz

- Active CPU current slope with 0.9-V core operation

? Cortex?-M4: 22 μA/MHz

? Cortex?-M0+: 15 μA/MHz

- Two DMA controllers with 16 channels each

? Memory subsystem

- 1-MB application flash, 32-KB auxiliary flash (AUXFlash), and 32-KB supervisory flash (SFlash); read-while-write

(RWW) support. Two 8-KB flash caches, one for each CPU.

- 288-KB SRAM with power and data retention control

- One-time-programmable (OTP) 1-Kb eFuse array

? Low-power 1.7-V to 3.6-V operation

- Six power modes for fine-grained power management

- Deep Sleep mode current of 7 μA with 64-KB SRAM retention

- On-chip Single-In Multiple Out (SIMO) DC-DC buck converter, <1 μA quiescent current

- Backup domain with 64 bytes of memory and real-time clock

? Flexible clocking options

- 8-MHz Internal Main Oscillator (IMO) with ±2% accuracy

- Ultra-low-power 32-kHz Internal Low-speed Oscillator (ILO)

- On-chip crystal oscillators (16 to 35 MHz, and 32 kHz)

- Phase-locked loop (PLL) for multiplying clock frequencies

- Frequency-locked loop (FLL) for multiplying IMO frequency

- Integer and fractional peripheral clock dividers

? Quad SPI (QSPI)/Serial Memory Interface (SMIF)

- Execute-In-Place (XIP) from external quad SPI Flash

- On-the-fly encryption and decryption

- 4-KB cache for greater XIP performance with lower power

- Supports single, dual, quad, dual-quad, and octal interfaces with throughput up to 640 Mbps

? Segment LCD drive

- Supports up to 99 segments and up to 8 commons