CY96F355中文資料英飛凌數(shù)據(jù)手冊(cè)PDF規(guī)格書

Features

■ Technology

? 0.18 μm CMOS

■ CPU

? F2MC-16FX CPU

? Up to 56 MHz internal, 17.8 ns instruction cycle time

? Optimized instruction set for controller applications (bit, byte,

word and long-word data types; 23 different addressing

modes; barrel shift; variety of pointers)

? 8-byte instruction execution queue

? Signed multiply (16-bit × 16-bit) and divide (32-bit/16-bit) instructions

available

■ System clock

? On-chip PLL clock multiplier (x1 - x25, x1 when PLL stop)

? 3 MHz - 16 MHz external crystal oscillator clock (maximum

frequency when using ceramic resonator depends on Q-factor).

? Up to 56 MHz external clock

? 32-100 kHz subsystem quartz clock

? 100 kHz/2 MHz internal RC clock for quick and safe startup,

oscillator stop detection, watchdog

? Clock source selectable from main- and subclock oscillator

(part number suffix “W”) and on-chip RC oscillator, independently

for CPU and 2 clock domains of peripherals.

? Low Power Consumption - 13 operating modes : (different

Run, Sleep, Timer modes, Stop mode)

? Clock modulator

■ On-chip voltage regulator

? Internal voltage regulator supports reduced internal MCU

voltage, offering low EMI and low power consumption figures

■ Low voltage reset

? Reset is generated when supply voltage is below minimum.

■ Code Security

? Protects ROM content from unintended read-out

■ Memory Patch Function

? Replaces ROM content

? Can also be used to implement embedded debug support

■ DMA

? Automatic transfer function independent of CPU, can be assigned

freely to resources

■ Interrupts

? Fast Interrupt processing

? 8 programmable priority levels

? Non-Maskable Interrupt (NMI)

■ Timers

? Three independent clock timers (23-bit RC clock timer, 23-bit

Main clock timer, 17-bit Sub clock timer)

? Watchdog Timer

■ CAN

? Supports CAN protocol version 2.0 part A and B

? ISO16845 certified

? Bit rates up to 1 Mbit/s

? 32 message objects

? Each message object has its own identifier mask

? Programmable FIFO mode (concatenation of message objects)

? Maskable interrupt

? Disabled Automatic Retransmission mode for Time Triggered

CAN applications

? Programmable loop-back mode for self-test operation

■ USART

? Full duplex USARTs (SCI/LIN)

? Wide range of baud rate settings using a dedicated reload

timer

? Special synchronous options for adapting to different synchronous

serial protocols

? LIN functionality working either as master or slave LIN device

■ I2C

? Up to 400 kbps

? Master and Slave functionality, 7-bit and 10-bit addressing

■ A/D converter

? SAR-type

? 10-bit resolution

? Signals interrupt on conversion end, single conversion mode,

continuous conversion mode, stop conversion mode, activation

by software, external trigger or reload timer