General description

CYT2BL is a family of TRAVEO? T2G microcontrollers targeted at automotive systems such as body control units.

CYT2BL has an Arm? Cortex?-M4 CPU for primary processing, and an Arm? Cortex?-M0+ CPU for peripheral and

security processing. These devices contain embedded peripherals supporting Controller Area Network with

Flexible Data rate (CAN FD), Local Interconnect Network (LIN), and Clock Extension Peripheral Interface (CXPI).

TRAVEO? T2G devices are manufactured on an advanced 40-nm process. CYT2BL incorporates a low-power flash

memory, multiple high-performance analog and digital peripherals, and enables the creation of a secure

computing platform.

Features

? Dual CPU subsystem

- 160-MHz (max) 32-bit Arm? Cortex?-M4F CPU with

? Single-cycle multiply

? Single-precision floating point unit (FPU)

? Memory protection unit (MPU)

- 100-MHz (max) 32-bit Arm? Cortex? M0+ CPU with

? Single-cycle multiply

? Memory protection unit

- Inter-processor communication in hardware

- Three DMA controllers

? Peripheral DMA controller #0 (P-DMA0) with 92 channels

? Peripheral DMA controller #1 (P-DMA1) with 44 channels

? Memory DMA controller #0 (M-DMA0) with 4 channels

? Integrated memories

- 4160 KB of code-flash with an additional 128 KB of work-flash

? Read-While-Write (RWW) allows updating the code-flash/work-flash while executing code from it

? Single- and dual-bank modes (specifically for Firmware update Over The Air [FOTA])

? Flash programming through SWD/JTAG interface

- 512 KB of SRAM with selectable retention granularity

? Crypto engine[1]

- Supports enhanced Secure Hardware Extension (eSHE) and Hardware Security Module (HSM)

- Secure boot and authentication

? Using digital signature verification

? Using fast secure boot

- AES: 128-bit blocks, 128-/192-/256-bit keys

- 3DES[2]: 64-bit blocks, 64-bit key

- Vector unit[2] supporting asymmetric key cryptography such as Rivest-Shamir-Adleman (RSA) and Elliptic

Curve (ECC)

- SHA-1/2/3[2]: SHA-512, SHA-256, SHA-160 with variable length input data

- CRC[2]: supports CCITT CRC16 and IEEE-802.3 CRC32

- True random number generator (TRNG) and pseudo random number generator (PRNG)

- Galois/Counter Mode (GCM)

? Functional safety for ASIL-B

- Memory protection unit (MPU)

- Shared memory protection unit (SMPU)

- Peripheral protection unit (PPU)

- Watchdog timer (WDT)

- Multi-counter watchdog timer (MCWDT)

- Low-voltage detector (LVD)

- Brown-out detector (BOD)

- Overvoltage detection (OVD)

- Clock supervisor (CSV)

- Hardware error correction (SECDED ECC) on all safety-critical memories (SRAM, flash)

? Low-power 2.7-V to 5.5-V operation

- Low-power Active, Sleep, Low-power Sleep, DeepSleep, and Hibernate modes for fine-grained power

management

- Configurable options for robust BOD

? Two threshold levels (2.7 V and 3.0 V) for BOD on VDDD and VDDA

? One threshold level (1.1 V) for BOD on VCCD

? Wakeup support

- Up to two pins to wakeup from Hibernate mode

- Up to 152 GPIO pins to wakeup from Sleep modes

- Event Generator, SCB, Watchdog Timer, RTC alarms to wake from DeepSleep modes

? Clock sources

- Internal main oscillator (IMO)

- Internal low-speed oscillator (ILO)

- External crystal oscillator (ECO)

- Watch crystal oscillator (WCO)

- Phase-locked loop (PLL)

- Frequency-locked loop (FLL)

? Communication interfaces

- Up to eight CAN FD channels

? Increased data rate (up to 8 Mbps) compared to classic CAN, limited by physical layer topology and

transceivers

? Compliant to ISO 11898-1:2015

? Supports all the requirements of Bosch CAN FD Specification V1.0 for non-ISO CAN FD

? ISO 16845:2015 certificate available

- Up to eight runtime-reconfigurable SCB (serial communication block) channels, each configurable as I2C, SPI,

or UART

- Up to 12 independent LIN channels

? LIN protocol compliant with ISO 17987

- Up to four CXPI channels with data rate up to 20 kbps

? Timers

- Up to 75 16-bit and eight 32-bit timer/counter pulse-width modulator (TCPWM) blocks

? Up to 12 16-bit counters for motor control

? Up to 63 16-bit counters and eight 32-bit counters for regular operations

? Supports timer, capture, quadrature decoding, pulse-width modulation (PWM), PWM with dead time (PWM_

DT), pseudo-random PWM (PWM_PR), and shift-register (SR) modes

- Up to 11 Event Generation (EVTGEN) timers supporting cyclic wakeup from DeepSleep

? Events trigger a specific device operation (such as execution of an interrupt handler, a SAR ADC conversion,

and so on)

? Real time clock (RTC)

- Year/month/date, day-of-week, Hour:Minute:Second fields

- Supports both 12- and 24-hour formats

- Automatic leap-year correction

? I/O

- Up to 152 programmable I/Os

- Two I/O types

? GPIO Standard (GPIO_STD)

? GPIO Enhanced (GPIO_ENH)

? Regulators

- Generates 1.1-V nominal core supply from a 2.7-V to 5.5-V input supply

- Two types of regulators

? DeepSleep

? Core internal

? Programmable analog

- Three SAR A/D converters with up to 67 external channels (64 I/Os + 3 I/Os for motor control)

? ADC0 supports 24 logical channels, with 24 + 1 physical connections

? ADC1 supports 32 logical channels, with 32 + 1 physical connections

? ADC2 supports 8 logical channels, with 8 + 1 physical connections

? Any external channel can be connected to any logical channel in the respective SAR

- Each ADC supports 12-bit resolution and sampling rates of up to 1 Msps

- Each ADC also supports up to six internal analog inputs such as:

? Bandgap reference to establish absolute voltage levels

? Calibrated diode for junction temperature calculations

? Two AMUXBUS inputs and two direct connections to monitor supply levels

- Each ADC supports addressing of external multiplexers

- Each ADC has a sequencer supporting autonomous scanning of configured channels

- Synchronized sampling of all ADCs for motor-sense applications

? Smart I/O

- Up to five Smart I/O blocks, which can perform Boolean operations on signals going to and from I/Os

- Up to 36 I/Os (GPIO_STD) supported

? Debug interface

- JTAG controller and interface compliant to IEEE-1149.1-2001

- Arm? serial wire debug (SWD) port

- Supports Arm? Embedded Trace Macrocell (ETM) Trace

? Data trace using SWD

? Instruction and data trace using JTAG

? Compatible with industry-standard tools

- GHS/MULTI or IAR EWARM for code development and debugging

? Packages

- 64-LQFP, 10 × 10 × 1.7 mm (max), 0.5-mm lead pitch

- 80-LQFP, 12 × 12 × 1.7 mm (max). 0.5-mm lead pitch

- 100-LQFP, 14 × 14 × 1.7 mm (max), 0.5-mm lead pitch

- 144-LQFP, 20 × 20 × 1.7 mm (max), 0.5-mm lead pitch

- 176-LQFP, 24 × 24 × 1.7 mm (max), 0.5-mm lead pitch