General description

CYT4BF is a family of TRAVEO? T2G microcontrollers targeted at automotive systems such as high-end

body-control units. CYT4BF has two Arm? Cortex?-M7 CPUs for primary processing, and an Arm?Cortex?-M0+ CPU

for peripheral and security processing. These devices contain embedded peripherals supporting Controller Area

Network with Flexible Data rate (CAN FD), Local Interconnect Network (LIN), Gigabit Ethernet, and FlexRay.

TRAVEO? T2G devices are manufactured on an advanced 40-nm process. CYT4BF incorporates a low-power flash

memory, multiple high-performance analog and digital peripherals, and enables the creation of a secure

computing platform.

Features

? CPU subsystem

- Two 350-MHz 32-bit Arm? Cortex?-M7 CPUs, each with

? Single-cycle multiply

? Single/double-precision floating point unit (FPU)

? 16-KB data cache, 16-KB instruction cache

? Memory protection unit (MPU)

? 16-KB instruction and 16-KB data tightly-coupled memories (TCM)

- 100-MHz 32-bit Arm? Cortex? M0+ CPU with

? Single-cycle multiply

? Memory protection unit (MPU)

- Inter-processor communication in hardware

- Three DMA controllers

? Peripheral DMA controller #0 (P-DMA0) with 143 channels

? Peripheral DMA controller #1 (P-DMA1) with 65 channels

? Memory DMA controller (M-DMA0) with 8 channels

? Integrated memories

- 8384 KB of code-flash with an additional 256 KB of work-flash

? Read-While-Write (RWW) allows updating the code-flash/work-flash while executing from it

? Single- and dual-bank modes (specifically for Firmware update Over The Air [FOTA])

? Flash programming through SWD/JTAG interface

- 1024-KB of SRAM with selectable retention granularity

? Cryptography engine

- Supports Enhanced Secure Hardware Extension (eSHE) and Hardware Security Module (HSM)

- Secure boot and authentication

? Using digital signature verification

? Using fast secure boot

- AES: 128-bit blocks, 128-/192-/256-bit keys

- 3DES: 64-bit blocks, 64-bit key

- Vector unit supporting asymmetric key cryptography such as Rivest-Shamir-Adleman (RSA) and Elliptic Curve

(ECC)

- SHA-1/2/3: SHA-512, SHA-256, SHA-160 with variable length input data

- CRC: supports CCITT CRC16 and IEEE-802.3 CRC32

- True random number generator (TRNG) and pseudo random number generator (PRNG)

- Galois/Counter Mode (GCM)

Features

? Functional safety for ASIL-B

- Memory protection unit (MPU)

- Shared memory protection unit (SMPU)

- Peripheral protection unit (PPU)

- Watchdog timer (WDT)

- Multi-counter watchdog timer (MCWDT)

- Low-voltage detector (LVD)

- Brown-out detection (BOD)

- Over-voltage detection (OVD)

- Clock supervisor (CSV)

- Hardware error correction (SECDED ECC) on all safety-critical memories (SRAM, flash, TCM)

? Low-Power 2.7-V to 5.5-V operation

- Low-power Active, Sleep, Low-power Sleep, DeepSleep, and Hibernate modes for fine-grained power

management

- Configurable options for robust BOD

? Two threshold levels (2.7 V and 3.0 V) for BOD on VDDD and VDDA

? One threshold level (1.1 V) for BOD on VCCD

? Wakeup

- Up to two pins to wake from Hibernate mode

- Up to 240 GPIO pins to wake from Sleep modes

- Event Generator, SCB, watchdog timer, RTC alarms to wake from DeepSleep modes

? Clocks

- Internal main oscillator (IMO)

- Internal low-speed oscillator (ILO)

- External crystal oscillator (ECO)

- Watch crystal oscillator (WCO)

- Phase-locked loop (PLL)

- Frequency-locked loop (FLL)

? Communication interfaces

- Up to 10 CAN FD channels

? Increased data rate (up to 8 Mbps) compared to classic CAN, limited by physical layer topology and

transceivers

? Compliant to ISO 11898-1:2015

? Supports all the requirements of Bosch CAN FD Specification V1.0 for non-ISO CAN FD

? ISO 16845:2015 certificate available

- Up to 11 runtime-reconfigurable SCB (serial communication block) channels, each configurable as I2C, SPI,

or UART

- Up to 20 independent LIN channels

? LIN protocol compliant with ISO 17987

- Up to two 10/100/1000 Mbps Ethernet MAC interfaces conforming to IEEE-802.3az

? Supports the following PHY interfaces:

Media-independent interface (MII)

Reduced media-independent interface (RMII)

Gigabit media-independent interface (GMII)

Reduced gigabit media-independent interface (RGMII)

? Compliant with IEEE-802.1BA Audio Video Bridging (AVB)

? Compliant with IEEE-1588 Precision Time Protocol (PTP)

- FlexRay interface (V2.1) configurable for single or dual data-channels for fault tolerance, supporting data rates up to 10 Mbps

? External memory interface

- One SPI (single, dual, quad, or octal) or HYPERBUS? interface

- On-the-fly encryption and decryption

- Execute-In-Place (XIP) from external memory

? SDHC interface

- One Secure Digital High Capacity (SDHC) interface supporting embedded MultiMediaCard (eMMC), Secure

Digital (SD), or SDIO (Secure Digital Input Output)

? Compliant to eMMC 5.1, SD 6.0, and SDIO 4.10 specifications

- Data rates up to SD High Speed 50 MHz, or eMMC 52 MHz DDR

? Audio interface

- Three Inter-IC Sound (I2S) Interfaces for connecting digital audio devices

- I2S, left justified, or time division multiplexed (TDM) audio formats

- Independent transmit or receive operation, each in master or slave mode

? Timers

- Up to 102 16-bit and 16 32-bit timer/counter pulse-width modulator (TCPWM) blocks

? Up to 15 16-bit counters for motor control

? Up to 87 16-bit counters and 16 32-bit counters for regular operations

? Supports timer, capture, quadrature decoding, pulse-width modulation (PWM), PWM with dead time

(PWM_DT), pseudo-random PWM (PWM_PR), and shift-register (SR) modes

- Up to 16 Event Generation (EVTGEN) timers supporting cyclic wakeup from DeepSleep

? Events trigger a specific device operation (such as execution of an interrupt handler, a SAR ADC conversion,

and so on)

? Real time clock (RTC)

- Year/Month/Date, Day-of-week, Hour:Minute:Second fields

- 12- and 24-hour formats

- Automatic leap-year correction

? I/O

- Up to 240 programmable I/Os

- Three I/O types

? GPIO Standard (GPIO_STD)

? GPIO Enhanced (GPIO_ENH)

? High-Speed I/O Standard (HSIO_STD)

? Regulators

- Generates a 1.1-V nominal core supply from a 2.7-V to 5.5-V input supply

- Three regulators:

? DeepSleep

? Core internal

? Core external

? Programmable analog

- Three SAR A/D converters with up to 99 external channels (96 I/Os + 3 I/Os for motor control)

? Each ADC supports 32 logical channels, with 32 + 1 physical connections. Any external channel can be

connected to any logical channel in the respective SAR.

- Each ADC supports 12-bit resolution and sampling rates of up to 1 Msps

- Each ADC also supports six internal analog inputs like

? Bandgap reference to establish absolute voltage levels

? Calibrated diode for junction temperature calculations

? Two AMUXBUS inputs and two direct connections to monitor supply levels

- Each ADC supports addressing of external multiplexers

- Each ADC has a sequencer supporting autonomous scanning of configured channels

- Synchronized sampling of all ADCs for motor-sense applications

Smart I/O

- Up to five Smart I/O blocks, which can perform Boolean operations on signals going to and from I/Os

- Up to 36 I/Os (GPIO_STD) supported

Debug interface

- JTAG controller and interface compliant to IEEE-1149.1-2001

- Arm? SWD (serial wire debug) port

- Supports Arm? Embedded Trace Macrocell (ETM) Trace

? Data trace using SWD

? Instruction and data trace using JTAG

Compatible with industry-standard tools

- GHS MULTI or IAR EWARM for code development and debugging

Packages

- 176-TEQFP, 24 × 24 × 1.7 mm (max), 0.5-mm lead pitch

- 272-BGA, 16 × 16 × 1.7 mm (max), 0.8-mm ball pitch

- 320-BGA, 17 × 17 × 1.7 mm (max), 0.8-mm ball pitch