D1028AN9CPGXN-U中文資料金士頓數(shù)據(jù)手冊PDF規(guī)格書

? Features

? Double-data-rate architecture: two data transfers per clock cycle.

? The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture.

? Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver.

? DQS is edge-aligned with data for READs; center- aligned with data for WRITEs.

? Differential clock inputs (CK_t and CK_c).

? DLL aligns DQ and DQS transitions with CK transitions.

? Data mask (DM) write data-in at the both rising and falling edges of the data strobe.

? Write Cycle Redundancy Code (CRC) is supported.

? Programmable preamble for read and write is supported.

? Programmable burst length 4/8 with both nibble sequential and interleave mode.

? BL switch on the fly.

? Driver strength selected by MRS.

? Dynamic On Die Termination supported.

? Two Termination States such as RTT_PARK and RTT_NOM switchable by ODT pin.

? Asynchronous RESET pin supported.

? ZQ calibration supported.

? Write Levelization supported.

? This product in compliance with the RoHS directive.

? Internal Vref DQ level generation is available.

? TCAR(Temperature Controlled Auto Refresh) mode is supported.

? LP ASR(Low Power Auto Self Refresh) mode is supported.

? Command Address (CA) Parity (command/address) mode is supported.

? Per DRAM Addressability (PDA).

? Fine granularity refresh is supported.

? Geardown Mode(1/2 rate, 1/4 rate) is supported.

? Self Refresh Abort is supported.

? Maximum power saving mode is supported.

? Banks Grouping is applied, and CAS to CAS latency(tCCD_L, tCCD_S) for the banks in the same or different bank group accesses are available.

? DMI pin support for write data masking and DBIdc functionality.