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D16550中文資料DCD數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

D16550
廠商型號(hào)

D16550

功能描述

Configurable UART with FIFO ver 2.08

文件大小

186.04 Kbytes

頁(yè)面數(shù)量

7 頁(yè)

生產(chǎn)廠商 Digital Core Design
企業(yè)簡(jiǎn)稱

DCD

中文名稱

Digital Core Design官網(wǎng)

原廠標(biāo)識(shí)
數(shù)據(jù)手冊(cè)

下載地址一下載地址二

更新時(shí)間

2025-1-8 22:30:00

D16550規(guī)格書(shū)詳情

OVERVIEW

The D16550 is a soft Core of a Universal Asynchronous Receiver/Transmitter (UART) functionally identical to the TL16C550A. The D16550 allows serial transmission in two modes: UART mode and FIFO mode. In FIFO mode internal FIFOs are activated allowing 16 bytes (plus 3 bits of error data per byte in the RCVR FIFO) to be stored in both receive and transmit directions. D16550 performs serial-toparallel conversion on data characters received from a peripheral device or a MODEM, and parallel-to-serial conversion on data characters received from the CPU.

KEY FEATURES

● Software compatible with 16450 and 16550 UARTs

● Configuration capability

● Separate configurable BAUD clock line

● Two modes of operation: UART mode and FIFO mode

● Majority Voting Logic

● In the FIFO mode transmitter and receiver are each buffered with 16 byte FIFO to reduce the number of interrupts presented to the CPU

● Adds or deletes standard asynchronous communication bits (start, stop, and parity) to or from the serial data

● In UART mode receiver and transmitter are double buffered to eliminate a need for precise synchronization between the CPU and serial data

● Independently controlled transmit, receive, line status, and data set interrupts

● False start bit detection

● 16 bit programmable baud generator

● MODEM control functions (CTS, RTS, DSR, DTR, RI, and DCD)

○ Fully programmable serial-interface characteristics:

○ 5-, 6-, 7-, or 8-bit characters

○ Even, odd, or no-parity bit generation and

○ 1-, 1?-, or 2-stop bit generation detection

○ Baud generation

● Complete status reporting capabilities

● Line break generation and detection. Internal diagnostic capabilities:

○ Loop-back controls for communications link fault isolation

○ Break, parity, overrun, framing error simulation

● Two DMA Modes allows single and multitransfer

● Technology independent HDL Source Code

● Full prioritized interrupt system controls

● Fully synthesizable static design with no internal tri-state buffers

APPLICATIONS

● Serial Data communications applications

● Modem interface

產(chǎn)品屬性

  • 型號(hào):

    D16550

  • 制造商:

    DCD

  • 制造商全稱:

    DCD

  • 功能描述:

    Configurable UART with FIFO ver 2.08

供應(yīng)商 型號(hào) 品牌 批號(hào) 封裝 庫(kù)存 備注 價(jià)格
DSP
2020+
FQFP100
80000
只做自己庫(kù)存,全新原裝進(jìn)口正品假一賠百,可開(kāi)13%增
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DSP
23+
NA/
626
優(yōu)勢(shì)代理渠道,原裝正品,可全系列訂貨開(kāi)增值稅票
詢價(jià)
TSMC
22+
QFP
100000
代理渠道/只做原裝/可含稅
詢價(jià)
DSP
24+
QFP
990000
明嘉萊只做原裝正品現(xiàn)貨
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DSP
23+
QFP
6850
只做原廠原裝正品現(xiàn)貨!假一賠十!
詢價(jià)
DSP
21+
FQFP100
626
原裝現(xiàn)貨假一賠十
詢價(jià)
DSP
2222+
FQFP100
4992
一級(jí)代理/分銷渠道價(jià)格優(yōu)勢(shì) 十年芯程一路只做原裝正品
詢價(jià)
DSP
24+
QFP
6980
原裝現(xiàn)貨,可開(kāi)13%稅票
詢價(jià)
DSP
23+
QFP
1075
專業(yè)優(yōu)勢(shì)供應(yīng)
詢價(jià)
TSMC
22+23+
QFP
28592
絕對(duì)原裝正品全新進(jìn)口深圳現(xiàn)貨
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