D555中文資料ALD數(shù)據(jù)手冊PDF規(guī)格書

GENERAL DESCRIPTION

The ALD555 timer is a high performance monolithic timing circuit built with advanced silicon gate CMOS technology. It offers the benefits of high input impedance, thereby allowing smaller timing capacitors and longer timing cycle; high speed, with typical cycle time of 500ns; low power dissipation for battery operated environment; reduced supply current spikes, allowing smaller and lower cost decoupling capacitors. It is capable of producing accurate time delays and oscillations in both monostable and astable operation. It operates in the one-shot (monostable) mode or 50 duty cycle free running oscillation mode with a single resistor and one capacitor. The inputs and outputs are fully compatible with CMOS, NMOS or TTL logic.

FEATURES

? Functional equivalent to NE555 with greatly expanded high and low frequency ranges

? High speed, low power, monolithic CMOS technology

? Low supply current 100μA typical

? Extremely low trigger, threshold and reset currents -- 1pA typical

? High speed operation -- 2MHz oscillation

? Low operating supply voltage 2 to 12V

? Operates in both monostable and astable modes

? Fixed 50 duty cycle or adjustable duty cycle CMOS, NMOS and TTL compatible input/output

? High discharge sinking current (80mA)

? Low supply current spikes

APPLICATIONS

? High speed one-shot (monostable) pulse generation

? Precision timing

? Sequential timing

? Long delay timer

? Pulse width and pulse position modulation

? Missing pulse detector

? Frequency divider