D8259中文資料DCD數(shù)據(jù)手冊(cè)PDF規(guī)格書

OVERVIEW

The D8259 is a soft Core of Programmable Interrupt Controller. It is fully compatible with the 82C59A device. The D8259 Core manages up to 8-vectored priority interrupts for processor. Programming it to cascade allows for up to 64 vectored interrupts. More than 64 vectored interrupts can be accomplished by programming to Poll Command Mode.

D8259 can operate in all 82C59A modes, and supports all 82C59A features:

● MCS-80/85 and 8088/8086 processor modes

● Fully nested mode and special fully nested mode

● Special mask mode

● Buffered mode

● Pool command mode

● Cascade mode with master or slave selection

● Automatic end-of-interrupt mode

● Specific and non-specific end-of-interrupt commands

● Automatic and Specific Rotation

● Edge and level triggered interrupt input modes

● Reading of interrupt request register (IIR) and in-service register (ISR) through data bus.

● Writing and reading of interrupt mask register (IMR) through data bus

KEY FEATURES

● 8 vectored priority interrupts

● Up to sixty-four vectored priority interrupts with cascading

● Support for all 82C59A modes features

○ MCS-80/85 and 8088/8086 processor modes

○ Fully nested mode and special fully nested mode

○ Special mask mode

○ Buffered mode

○ Pool command mode

○ Cascade mode with master or slave selection

○ Automatic end-of-interrupt mode

○ Specific and non-specific end-of-interrupt commands

○ Automatic and Specific Rotation

○ Edge and level triggered interrupt input modes

○ Reading of interrupt request register (IIR) and in-service register (ISR) through data bus

● Fully synthesizable, static design with no internal tri-states