DAC1628D1G25HN中文資料瑞薩數(shù)據(jù)手冊PDF規(guī)格書

Dual channel 16-bit resolution

1.25 Gsps maximum output update rate

JEDEC JESD204B device subclass I

compliant: SYSREF based deterministic

and repeatable interface latency

Multiple Device Synchronization (MDS,

a unique CGVxpress feature) enables

up to 16 DAC channels to be sample

synchronous and phase coherent to

within one DAC clock period

1, 2 or 4 configurable JESD204B serial

input lanes running up to 6.25 Gbps with

embedded termination and

programmable equalization

625 Msps maximum baseband input

data rate

SPI interface (3-wire or 4-wire mode) for

control setting and status monitoring

Differential scalable output current from

8.1 mA to 34 mA

Embedded NCO with 40-bit

programmable frequency and 16-bit

phase adjustment

Embedded complex (IQ) digital

modulator

1.8 V and 3.3 V power supplies