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DDU8C3-5100中文資料DATADELAY數(shù)據(jù)手冊(cè)PDF規(guī)格書

DDU8C3-5100
廠商型號(hào)

DDU8C3-5100

功能描述

5-TAP, 3.3V CMOS-INTERFACED FIXED DELAY LINE

文件大小

45.78 Kbytes

頁面數(shù)量

4

生產(chǎn)廠商 Data Delay Devices, Inc.
企業(yè)簡稱

DATADELAY

中文名稱

Data Delay Devices, Inc.官網(wǎng)

原廠標(biāo)識(shí)
數(shù)據(jù)手冊(cè)

下載地址一下載地址二

更新時(shí)間

2024-11-17 22:59:00

DDU8C3-5100規(guī)格書詳情

FUNCTIONAL DESCRIPTION

The DDU8C3-series device is a 5-tap digitally buffered delay line. The signal input (IN) is reproduced at the outputs (T1-T5), shifted in time by an amount determined by the device dash number (See Table). For dash numbers 5020 and above, the total delay of the line is measured from IN to T5, and the nominal tap-to-tap delay increment is given by one-fifth of the total delay. For dash numbers below 5020, the total delay is measured from T1 to T5, and the delay increment is given by one-fourth of the total delay.

FEATURES

? Five equally spaced outputs

? Fits standard 8-pin DIP socket

? Low profile

? Auto-insertable

? Input & outputs fully CMOS interfaced & buffered

? 10 T2L fan-out capability

產(chǎn)品屬性

  • 型號(hào):

    DDU8C3-5100

  • 功能描述:

    5-TAP, 3.3V CMOS-INTERFACED FIXED DELAY LINE

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23+
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