DSP56300FM中文資料恩智浦數(shù)據(jù)手冊PDF規(guī)格書

Features

? Up to 150 million multiply-accumulates per second (MMACS) (300 MMACS using the EFCOP in filtering

applications) with a 150 MHz clock at 1.8 V core and 3.3 V I/O

? Object code compatible with the DSP56000 core with highly parallel instruction set

? Data arithmetic logic unit (Data ALU) with fully pipelined 24 × 24-bit parallel Multiplier-Accumulator (MAC),

56-bit parallel barrel shifter (fast shift and normalization; bit stream generation and parsing), conditional

ALU instructions, and 24-bit or 16-bit arithmetic support under software control

? Program control unit (PCU) with position-independent code (PIC) support, addressing modes optimized for

DSP applications (including immediate offsets), internal instruction cache controller, internal memoryexpandable

hardware stack, nested hardware DO loops, and fast auto-return interrupts

? Direct memory access (DMA) with six DMA channels supporting internal and external accesses; one-, two-

, and three-dimensional transfers (including circular buffering); end-of-block-transfer interrupts; and

triggering from interrupt lines and all peripherals

? Phase-lock loop (PLL) allows change of low-power divide factor (DF) without loss of lock and output clock

with skew elimination

? Hardware debugging support including on-chip emulation (OnCE‘) module, Joint Test Action Group (JTAG)

test access port (TAP)

Applications

DSP56311 applications require high performance, low power, small packaging, and a large amount of internal

memory. The EFCOP can accelerate general filtering applications. Examples include:

? Wireless and wireline infrastructure applications

? Multi-channel wireless local loop systems

? DSP resource boards

? High-speed modem banks

? IP telephony