EDI7F328XDNSN中文資料WEDC數(shù)據(jù)手冊PDF規(guī)格書

General Description

The EDI7F328XDNSN and EDI7F2328XDNSN are organized as one and two banks of 8M x 32 respectively. The modules are based on Intels E28F640J3, 8M x 8 / 4M x 16 device family. Both modules offer access times of 120-150ns

Features

● 8M x 32 and 2 x 8M x 32 Densities

● Based on Intels Strataflash (J3) family of Flash Devices

○ E28F640J3

● (64) 128Kb Erase Blocks (Symetrical)

● High Performance Interface Async Page Mode Reads

○ 120/25 ns Read Access Time

● 2.7V - 3.6V Vcc Operation

● 128 bit Protection Register;

○ 64 bit Unique Device Identifier

○ 64 bit User Programmable OTP Cells

● Common Flash Interface (CFI)

● Scaleable Command Set (SCS)

● 32 byte Write Buffer, 64M Total Erase Cycles

○ 100,000 Erase Cycles per Block

● Package

○ 80 pin SIMM