EDI88128CXCC中文資料WEDC數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

The EDI88128C is a high speed, high performance, Monolithic CMOS Static RAM organized as 128Kx8. The device is also available as EDI88130C with an additional chip select line (CS2) which will automatically power down the device when proper logic levels are applied.

The second chip select line (CS2) can be used to provide system memory security during power down in non-battery backed up systems and simplifi y decoding schemes in memory banking where large multiple pages of memory are required.

The EDI88128C and the EDI88130C have eight bidirectional input-output lines to provide simultaneous access to all bits in a word. An automatic power down feature permits the on-chip circuitry to enter a very low standby mode and be brought back into operation at a speed equal to the address access time.

FEATURES

■ Access Times of 70, 85, 100ns

■ Available with Single Chip Selects (EDI88128) or Dual Chip Selects (EDI88130)

■ 2V Data Retention (LP Versions)

■ CS# and OE# Functions for Bus Control

■ TTL Compatible Inputs and Outputs

■ Fully Static, No Clocks

■ Organized as 128Kx8

■ Industrial, Military and Commercial Temperature Ranges

■ Thru-hole and Surface Mount Packages JEDEC Pinout

? 32 pin Ceramic DIP, 0.6 mils wide (Package 9)

? 32 lead Ceramic SOJ (Package 140)

■ Single +5V (±10) Supply Operation