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EDI88512CXNM中文資料WEDC數(shù)據(jù)手冊PDF規(guī)格書

EDI88512CXNM
廠商型號

EDI88512CXNM

功能描述

512Kx8 Monolithic SRAM, CMOS

文件大小

319.8 Kbytes

頁面數(shù)量

7

生產(chǎn)廠商 White Electronic Designs Corporation
企業(yè)簡稱

WEDC

中文名稱

White Electronic Designs Corporation

原廠標識
數(shù)據(jù)手冊

下載地址一下載地址二

更新時間

2024-11-16 14:32:00

EDI88512CXNM規(guī)格書詳情

The EDI88512C is a 4 megabit Monolithic CMOS Static RAM.

The 32 pin DIP pinout adheres to the JEDEC evolutionary standard for the four megabit device. Both the DIP and CSOJ packages are pin for pin upgrades for the single chip enable 128K x 8, the EDI88128C. Pins 1 and 30 become the higher order addresses.

A Low Power version with Data Retention (EDI88512LP) is also available for battery backed applications. Military product is available compliant to Appendix A of MIL-PRF-38535.

FEATURES

■ 512Kx8 bit CMOS Static

■ Random Access Memory

? Access Times of 70, 85, 100ns

? Data Retention Function (LP version)

? TTL Compatible Inputs and Outputs

? Fully Static, No Clocks

■ 32 lead JEDEC Approved Evolutionary Pinout

? Ceramic Sidebrazed 600 mil DIP (Package 9)

? Ceramic SOJ (Package 140)

■ Single +5V (±10) Supply Operation

產(chǎn)品屬性

  • 型號:

    EDI88512CXNM

  • 制造商:

    WEDC

  • 制造商全稱:

    White Electronic Designs Corporation

  • 功能描述:

    512Kx8 Monolithic SRAM, CMOS

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