EDI8L24128C12BI中文資料WEDC數(shù)據(jù)手冊(cè)PDF規(guī)格書

DESCRIPTION

The EDI8L24128CxxBC is a 5V, three megabit SRAM constructed with three 128Kx8 die mounted on a multilayer laminate substrate. With 12 to 15ns access times, x24 width and a 5V operating voltage, the EDI8L2418C is ideal for creating a single chip memory solution for the Motorola DSP5600x or a two chip solution for the Analog Devices SHARC? DSP.

The single or dual chip memory solutions offer improved system performance by reducing the length of board traces and the number of board connections compared to using multiple monolithic devices. For example, the capacitance load on the data lines for the BGA package is 58 less than a monolithic SOJ solution.

The JEDEC Standard 119 lead BGA provides a 44 space savings over using 128Kx8, 300mm wide SOJs and the BGA package has a height of 100mm compared to 148mm for the SOJ packages.

FEATURES

■ 128Kx24 bit CMOS Static

■ Random Access Memory Array

■ Fast Access Times: 12 and 15ns

■ Master Output Enable and Write Control

■ TTL Compatible Inputs and Outputs

■ Fully Static, No Clocks

■ Surface Mount Package

■ 119 Lead BGA (JEDEC MO-163), No. 391

■ Small Footprint, 14mm x 22mm

■ Multiple Ground Pins for Maximum Noise Immunity

■ Single +5V (±10) Supply Operation

■ DSP Memory Solution

■ Motorola DSP5600x?

■ Analog Devices SHARC?