EDS2508ACTA-75中文資料美光科技數(shù)據(jù)手冊PDF規(guī)格書

Description

The EDS2504AC/AP is a 256M bits SDRAM organized as 16,777,216 words × 4 bits × 4 banks. The EDS2508 AC/AP is a 256M bits SDRAM organized as 8,388,608 words × 8 bits × 4 banks. The EDS2516 AC/AP is a 256M bits SDRAM organized as 4194304 words × 16 bits × 4 banks. All inputs and outputs are referred to the rising edge of the clock input. It is packaged in standard 54-pin plastic TSOP (II).

Features

? 3.3V power supply

? Clock frequency: 133MHz (max.)

? LVTTL interface

? Single pulsed /RAS

? 4 banks can operate simultaneously and independently

? Burst read/write operation and burst read/single write operation capability

? Programmable burst length* (BL): 1, 2, 4, 8

? 2 variations of burst sequence

? - Sequential (BL = 1, 2, 4, 8)

? - Interleave (BL = 1, 2, 4, 8)

? Programmable /CAS latency (CL): 2, 3

? Byte control by DQM

: DQM (EDS2504AC/AP, EDS2508AC/AP)

: UDQM, LDQM (EDS2516AC/AP)

? Refresh cycles: 8192 refresh cycles/64ms

? 2 variations of refresh

? - Auto refresh

? - Self refresh