EL2019中文資料Intersil數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

The EL2019 offers a new feature previously unavailable in a comparator before—a master/slave edge triggered flip-flop. The comparator output will only change output state after a positive going clock edge is applied. Thus the output cant feed back to the input and cause oscillation.

Features

? Comparator cannot oscillate

? Fast response—5ns data to clock setup, 20ns clock to output

? Wide input differential voltage range—24V on ±15V supplies

? Wide input common mode voltage range—±12V

? Precision input stage—VOS = 1.5mV

? Low input bias current—100nA

? Low input offset current—30nA

? ±4.5V to ±18V supplies

? Three-State TTL compatible output

? No supply current glitch during switching

? 103dB voltage gain (Low input uncertainty ≈ 30μV)

? 50 power reduction in shut-down mode

? Input and flip-flop remain active in shutdown mode

Applications

? Analog to digital converters

? ATE pin receiver

? Zero crossing detector

? Window detector

? “Go/no-go” detector