EPL2014-102ML中文資料亞德諾數(shù)據(jù)手冊PDF規(guī)格書

GENERAL DESCRIPTION

The ADP5024 combines two high performance buck regulators and one low dropout (LDO) regulator in a small, 24-lead, 4 mm × 4 mm LFCSP to meet demanding performance and board space requirements.

The high switching frequency of the buck regulators enables tiny multilayer external components and minimizes the board space. When the MODE pin is set high, the buck regulators operate in forced PWM mode. When the MODE pin is set low, the buck regulators operate in PWM mode when the load current is above a predefined threshold. When the load current falls below a predefined threshold, the regulator operates in power save mode (PSM), improving the light load efficiency.

FEATURES

Main input voltage range: 2.3 V to 5.5 V

Two 1200 mA buck regulators and one 300 mA LDO

24-lead, 4 mm × 4 mm LFCSP package

Regulator accuracy: ±1.8

Factory programmable or external adjustable VOUTx

3 MHz buck operation with forced PWM and automatic

PWM/PSM modes

BUCK1/BUCK2: output voltage range from 0.8 V to 3.8 V

LDO: output voltage range from 0.8 V to 5.2 V

LDO: input supply voltage from 1.7 V to 5.5 V

LDO: high PSRR and low output noise

APPLICATIONS

Power for processors, ASICS, FPGAs, and RF chipsets

Portable instrumentation and medical devices

Space constrained devices