EPM7032B集成電路（IC）的CPLD（復(fù)雜可編程邏輯器件）規(guī)格書PDF中文資料

General Description

MAX 7000B devices are high-density, high-performance devices based on Altera’s second-generation MAX architecture. Fabricatedwith advanced CMOS technology, the EEPROM-based MAX 7000B devices operate with a 2.5-V supply voltage and provide 600 to 10,000 usable gates, ISP, pin-to-pin delays as fast as 3.5 ns, and counter speeds up to 303.0 MHz.

Features...

■ High-performance 2.5-V CMOS EEPROM-based programmable logic devices (PLDs) built on second-generation Multiple Array MatriX (MAX?) architecture (see Table 1)

– Pin-compatible with the popular 5.0-V MAX 7000S and 3.3-V MAX 7000A device families

– High-density PLDs ranging from 600 to 10,000 usable gates

– 3.5-ns pin-to-pin logic delays with counter frequencies in excess of 303.0 MHz

■ Advanced 2.5-V in-system programmability (ISP)

– Programs through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with advanced pin-locking capability

– Enhanced ISP algorithm for faster programming

– ISP_Done bit to ensure complete programming

– Pull-up resistor on I/O pinsduring in-system programming

– ISP circuitry compliant with IEEE Std. 1532

■ System-level features

–MultiVoltTM I/O interface enabling device core to run at 2.5 V, while I/O pins are compatible with3.3-V, 2.5-V, and 1.8-V logic levels

– Programmable power-saving mode for 50or greater power reduction in each macrocell

– Fast input setup times provided by a dedicated path from I/O pin to macrocell registers

– Support for advanced I/O standards, including SSTL-2 and SSTL-3, and GTL+

– Bus-hold option on I/O pins

– PCI compatible

– Bus-friendly architecture including programmable slew-rate control

– Open-drain output option

– Programmable security bit for protection of proprietary designs

– Built-in boundary-scan testcircuitry compliant with IEEE Std. 1149.1

– Supports hot-socketing operation

– Programmable ground pins

■ Advanced architecture features

– Programmable interconnect array (PIA) continuous routing structure for fast, predictable performance

– Configurable expander product-term distribution, allowing up to 32 product terms per macrocell

– Programmable macrocell registers with individual clear, preset, clock, and clock enable controls

– Two global clock signals with optional inversion

– Programmable power-up states for macrocell registers

– 6 to 10 pin- or logic-driven output enable signals

■ Advanced package options

– Pin counts ranging from 44 to 256 ina variety of thin quad flat pack (TQFP), plastic quad flatpack (PQFP), ball-grid array (BGA), space-saving FineLine BGATM, 0.8-mm Ultra FineLine BGA, and plastic J-lead chip carrier (PLCC) packages

– Pin-compatibility with other MAX 7000B devices in the same package

■ Advanced software support

– Software design support and automatic place-and-route provided by Altera’s MAX+PLUS? II development system for Windows-based PCs and Sun SPARCstation, and HP 9000 Series 700/800 workstations

– Additional design entry and simulation support provided by EDIF 2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPMs), Verilog HDL, VHDL, and other interfaces to popular EDA tools from manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity, and VeriBest

– Programming support with Altera’s Master Programming Unit (MPU), MasterBlasterTM serial/universal serial bus (USB) communications cable, and ByteBlasterMVTM parallel port download cable, as well as programming hardware from third party manufacturers and any JamTM STAPL File (.jam), Jam Byte Code File (.jbc), or Serial Vector Format File (.svf)-capable in circuit tester