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EPM7064S集成電路(IC)的CPLD(復(fù)雜可編程邏輯器件)規(guī)格書PDF中文資料

EPM7064S
廠商型號(hào)

EPM7064S

參數(shù)屬性

EPM7064S 封裝/外殼為44-LCC(J 形引線);包裝為托盤;類別為集成電路(IC)的CPLD(復(fù)雜可編程邏輯器件);產(chǎn)品描述:IC CPLD 64MC 10NS 44PLCC

功能描述

Programmable Logic Device Family

文件大小

1.49779 Mbytes

頁(yè)面數(shù)量

66 頁(yè)

生產(chǎn)廠商 Altera Corporation
企業(yè)簡(jiǎn)稱

Altera阿爾特

中文名稱

阿爾特拉公司官網(wǎng)

原廠標(biāo)識(shí)
數(shù)據(jù)手冊(cè)

下載地址一下載地址二到原廠下載

更新時(shí)間

2024-12-22 22:38:00

EPM7064S規(guī)格書詳情

General Description

The MAX 7000 family of high-density, high-performance PLDs is based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based MAX 7000 family provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counter speeds of up to 175.4 MHz. MAX 7000S devices in the -5, -6, -7, and -10 speed grades as well as MAX 7000 and MAX 7000E devices in -5, -6, -7, -10P, and -12P speed grades comply with the PCI Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2. See Table 3 for available speed grades.

The MAX 7000E devices—including the EPM7128E, EPM7160E, EPM7192E, and EPM7256E devices—have several enhanced features: additional global clocking, additional output enable controls, enhanced interconnect resources, fast input registers, and a programmable slew rate.

In-system programmable MAX 7000 devices—called MAX 7000S devices—include the EPM7032S, EPM7064S, EPM7128S, EPM7160S, EPM7192S, and EPM7256S devices. MAX 7000S devices have the enhanced features of MAX 7000E devices as well as JTAG BST circuitry in devices with 128 or more macrocells, ISP, and an open-drain output option. See Table 4.

Features...

■ High-performance, EEPROM-based programmable logic devices (PLDs) based on second-generation MAX? architecture

■ 5.0-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in MAX 7000S devices

– ISP circuitry compatible with IEEE Std. 1532

■ Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S devices

■ Built-in JTAG boundary-scan test (BST) circuitry in MAX 7000S devices with 128 or more macrocells

■ Complete EPLD family with logic densities ranging from 600 to 5,000 usable gates (see Tables 1 and 2)

■ 5-ns pin-to-pin logic delays with up to 175.4-MHz counter frequencies (including interconnect)

■ PCI-compliant devices available

■ Open-drain output option in MAX 7000S devices

■ Programmable macrocell flipflops with individual clear, preset, clock, and clock enable controls

■ Programmable power-saving mode for a reduction of over 50 in each macrocell

■ Configurable expander product-term distribution, allowing up to 32 product terms per macrocell

■ 44 to 208 pins available in plastic J-lead chip carrier (PLCC), ceramic pin-grid array (PGA), plastic quad flat pack (PQFP), power quad flat pack (RQFP), and 1.0-mm thin quad flat pack (TQFP) packages

■ Programmable security bit for protection of proprietary designs

■ 3.3-V or 5.0-V operation

– MultiVoltTM I/O interface operation, allowing devices to interface with 3.3-V or 5.0-V devices (MultiVolt I/O operation is not available in 44-pin packages)

– Pin compatible with low-voltage MAX 7000A and MAX 7000B devices

■ Enhanced features available in MAX 7000E and MAX 7000S devices

– Six pin- or logic-driven output enable signals

– Two global clock signals with optional inversion

– Enhanced interconnect resources for improved routability

– Fast input setup times provided by a dedicated path from I/O pin to macrocell registers

– Programmable output slew-rate control

■ Software design support and automatic place-and-route provided by Altera’s development system for Windows-based PCs and Sun SPARCstation, and HP 9000 Series 700/800 workstations

■ Additional design entry and simulation support provided by EDIF 2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM), Verilog HDL, VHDL, and other interfaces to popular EDA tools from manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, and VeriBest

■ Programming support

– Altera’s Master Programming Unit (MPU) and programming hardware from third-party manufacturers program all MAX 7000 devices

– The BitBlaster? serial download cable, ByteBlasterMV? parallel port download cable, and MasterBlaster? serial/universal serial bus (USB) download cable program MAX 7000S devices

產(chǎn)品屬性

  • 產(chǎn)品編號(hào):

    EPM7064SLC44-10F

  • 制造商:

    Intel

  • 類別:

    集成電路(IC) > CPLD(復(fù)雜可編程邏輯器件)

  • 系列:

    MAX? 7000S

  • 包裝:

    托盤

  • 可編程類型:

    系統(tǒng)內(nèi)可編程

  • 供電電壓 - 內(nèi)部:

    4.75V ~ 5.25V

  • 工作溫度:

    0°C ~ 70°C(TA)

  • 安裝類型:

    表面貼裝型

  • 封裝/外殼:

    44-LCC(J 形引線)

  • 供應(yīng)商器件封裝:

    44-PLCC(16.59x16.59)

  • 描述:

    IC CPLD 64MC 10NS 44PLCC

供應(yīng)商 型號(hào) 品牌 批號(hào) 封裝 庫(kù)存 備注 價(jià)格
ALTERA/阿爾特拉
23+
PLCC-44
30000
原裝正品公司現(xiàn)貨,假一賠十!
詢價(jià)
ALTERA/阿爾特拉
23+
BGA
2000
原廠原裝正品現(xiàn)貨
詢價(jià)
ALT
2018+
QFP
26976
代理原裝現(xiàn)貨/特價(jià)熱賣!
詢價(jià)
ALTERA/阿爾特拉
21+
TQFP
1680
只做原裝,質(zhì)量保證
詢價(jià)
ALT
24+
52
詢價(jià)
N/A
22+
NA
164126
原裝正品現(xiàn)貨,可開13個(gè)點(diǎn)稅
詢價(jià)
ALTERA
19+
QFP44
70483
原廠代理渠道,每一顆芯片都可追溯原廠;
詢價(jià)
IC
22+
原廠原封
327
全新原裝現(xiàn)貨!自家?guī)齑?
詢價(jià)
ALTERA/INTEL
2021
BGA
1000
全新、原裝
詢價(jià)
ALTERA
23+
TQFP
5000
原裝正品,假一罰十
詢價(jià)