EVAL-AD7960FMCZ開發(fā)板套件編程器的評(píng)估板-模數(shù)轉(zhuǎn)換器（ADC）規(guī)格書PDF中文資料

EVAL-AD7960FMCZ屬于開發(fā)板套件編程器的評(píng)估板-模數(shù)轉(zhuǎn)換器（ADC）。由亞德諾半導(dǎo)體技術(shù)有限公司制造生產(chǎn)的EVAL-AD7960FMCZ評(píng)估板 - 模數(shù)轉(zhuǎn)換器（ADC）模數(shù)轉(zhuǎn)換器 (ADC) 評(píng)估板是預(yù)裝有元器件的電路板，用于提供特定 ADC 或器件工作實(shí)例。特定板上的 A/D 轉(zhuǎn)換器數(shù)量從 3 到 32 不等，每秒采樣率從 2.5 kHz 到 26 GHz 不等，輸入電壓范圍從 0 到 8 Vp-p。

GENERAL DESCRIPTION

The AD7960 is an 18-bit, 5 MSPS, charge redistribution successive approximation (SAR), analog-to-digital converter (ADC). The SAR architecture allows unmatched performance both in noise and in linearity. The AD7960 contains a low power, high speed, 18-bit sampling ADC, an internal conversion clock, and an internal reference buffer. On the CNV± edge, the AD7960 samples the voltage difference between the IN+ and IN? pins.

FEATURES

Throughput: 5 MSPS

18-bit resolution with no missing codes

Excellent ac and dc performance

Dynamic range: 100 dB

SNR: 99 dB

THD: ?117 dB

INL: ±0.8 LSB (typical), ±2 LSB (maximum)

DNL: ±0.5 LSB (typical), ±0.99 LSB (maximum)

True differential analog input voltage range: ±4.096 V or ±5 V

Low power dissipation

46.5 mW at 5 MSPS with external reference buffer

(echoed clock mode)

64.5 mW at 5 MSPS with internal reference buffer

(echoed clock mode)

39 mW at 5 MSPS with external reference buffer

(self clocked mode, CNV± in CMOS mode)

SAR architecture

No latency/pipeline delay

External reference options: 2.048 V buffered to 4.096 V (internal

reference buffer), 4.096 V, and 5 V

Serial LVDS interface

Self clocked mode

Echoed clock mode

LVDS or CMOS option for conversion control (CNV± signal)

Operating temperature range of ?40°C to +85°C

32-lead, 5 mm × 5 mm LFCSP (QFN)

APPLICATIONS

Digital imaging systems

Digital X-rays

Computed tomography

IR cameras

MRI gradient control

High speed data acquisition

Spectroscopy

Test equipment