FDV302中文資料仙童半導(dǎo)體數(shù)據(jù)手冊PDF規(guī)格書

General Description

This P-Channel logic level enhancement mode field effect transistor is produced using Fairchilds proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. This device has been designed especially for low voltage applications as a replacement for digital transistors. Since bias resistors are not required, this one P-channel FET can replace several digital transistors with different bias resistors such as the DTCx and DCDx series.

Features

■ -25 V, -0.12 A continuous, -0.5 A Peak.

RDS(ON) = 13 W @ VGS= -2.7 V

RDS(ON) = 10 W @ VGS = -4.5 V.

■ Very low level gate drive requirements allowing direct

operation in 3V circuits. VGS(th) < 1.5V.

■ Gate-Source Zener for ESD ruggedness.

>6kV Human Body Model

■ Compact industry standard SOT-23 surface mount

package.

■ Replace many PNP digital transistors (DTCx and DCDx)

with one DMOS FET.