FW801BF-09-DB中文資料agere數(shù)據(jù)手冊(cè)PDF規(guī)格書

Description

The Agere Systems FW801BF device provides the analog physical layer functions needed to implement a one-port node in a cable-based IEEE 1394-1995 and IEEE 1394a-2000 network.

Distinguishing Features

■ Compliant with IEEE? Standard 1394a-2000, IEEE Standard for a High Performance Serial Bus Amendment 1.

■ Low power consumption during powerdown or microlow-power sleep mode.

■ Supports extended BIAS_HANDSHAKE time for enhanced interoperability with camcorders.

■ While unpowered and connected to the bus, will not drive TPBIAS on a connected port even if receiving incoming bias voltage on that port.

■ Does not require external filter capacitors for PLL.

■ Does not require a separate 5 V supply for 5 V link controller interoperability.

■ Interoperable across 1394 cable with 1394 physical layers (PHY) using 5 V supplies.

■ Interoperable with 1394 link-layer controllers using 5 V supplies.

■ 1394a-2000 compliant common mode noise filter on incoming TPBIAS.

■ Powerdown features to conserve energy in battery-powered applications include the following:

— Device powerdown ball.

— Link interface disable using LPS.

— Inactive ports power down.

— Automatic microlow-power sleep mode during suspend.

■ Interface to link-layer controller supports Annex J electrical isolation as well as bus-keeper isolation.

Features

■ Provides one fully compliant cable port at 100 Mbits/s, 200 Mbits/s, and 400 Mbits/s.

■ Fully supports 1394 Open HCI requirements.

■ Supports arbitrated short bus reset to improve utilization of the bus.

■ Supports ack-accelerated arbitration and fly-by concatenation.

■ Supports connection debounce.

■ Supports multispeed packet concatenation.

■ Supports PHY pinging and remote PHY access packets.

■ Fully supports suspend/resume.

■ Supports PHY-link interface initialization and reset.

■ Supports 1394a-2000 register set.

■ Supports LPS/link-on as a part of PHY-link interface.

■ Supports provisions of IEEE 1394-1995 Standard for a High Performance Serial Bus.

■ Fully interoperable with FireWire? and i.LINK? implementations of IEEE 1394-1995.

■ Reports cable power fail interrupt when voltage at CPS ball falls below 7.5 V.

■ Provides separate cable bias and driver termination voltage supply for port.

Other Features

■ 48-ball VTFSBGAC package.

■ Single 3.3 V supply operation.

■ Data interface to link-layer controller provided through 2/4/8 parallel lines at 50 Mbits/s.

■ 25 MHz crystal oscillator and PLL provide a 50 MHz link-layer controller clock as well as transmit/receive data at 100 Mbits/s, 200 Mbits/s, and 400 Mbits/s.

■ Multiple separate package signals provided for analog and digital supplies and grounds.