GAL22V10D-15LP集成電路（IC）的CPLD（復(fù)雜可編程邏輯器件）規(guī)格書(shū)PDF中文資料

Description

The GAL22V10, at 4ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest performance available of any 22V10 device on the market. CMOS circuitry allows the GAL22V10 to consume much less power when compared to bipolar 22V10 devices. E2 technology offers high speed (

Features

? HIGH PERFORMANCE E2CMOS? TECHNOLOGY

— 4 ns Maximum Propagation Delay

— Fmax = 250 MHz

— 3.5 ns Maximum from Clock Input to Data Output

— UltraMOS? Advanced CMOS Technology

? ACTIVE PULL-UPS ON ALL PINS

? COMPATIBLE WITH STANDARD 22V10 DEVICES

— Fully Function/Fuse-Map/Parametric Compatible with Bipolar and UVCMOS 22V10 Devices

? 50 to 75 REDUCTION IN POWER VERSUS BIPOLAR

— 90mA Typical Icc on Low Power Device

— 45mA Typical Icc on Quarter Power Device

? E2 CELL TECHNOLOGY

— Reconfigurable Logic

— Reprogrammable Cells

— 100 Tested/100 Yields

— High Speed Electrical Erasure (<100ms)

— 20 Year Data Retention

? TEN OUTPUT LOGIC MACROCELLS

— Maximum Flexibility for Complex Logic Designs

? PRELOAD AND POWER-ON RESET OF REGISTERS

— 100 Functional Testability

? APPLICATIONS INCLUDE:

— DMA Control

— State Machine Control

— High Speed Graphics Processing

— Standard Logic Speed Upgrade

? ELECTRONIC SIGNATURE FOR IDENTIFICATION