GAL26CLV12D-7LJ中文資料萊迪思數(shù)據(jù)手冊PDF規(guī)格書

Description

The GAL26CLV12D, at 5 ns maximum propagation delay time, provides higher performance than its 5V counterpart. The GAL26CLV12D can interface with both 3.3V and 5V signal levels. The GAL26CLV12D is manufactured using Lattice Semiconductors advanced 3.3V E2CMOS process, which combines CMOS with Electrically Erasable (E2) floating gate technology. High speed erase times (

Features

? HIGH PERFORMANCE E2CMOS? TECHNOLOGY

— 5 ns Maximum Propagation Delay

— Fmax = 200 MHz

— 3.5 ns Maximum from Clock Input to Data Output

— UltraMOS? Advanced CMOS Technology

? 3.3V LOW VOLTAGE 26CV12 ARCHITECTURE

— JEDEC-Compatible 3.3V Interface Standard

— Inputs and I/O Interface with Standard 5V TTL Devices

? ACTIVE PULL-UPS ON ALL PINS

? E2 CELL TECHNOLOGY

— Reconfigurable Logic

— Reprogrammable Cells

— 100 Tested/100 Yields

— High Speed Electrical Erasure (<100ms)

— 20 Year Data Retention

? TWELVE OUTPUT LOGIC MACROCELLS

— Maximum Flexibility for Complex Logic Designs

— Programmable Output Polarity

? PRELOAD AND POWER-ON RESET OF ALL REGISTERS

— 100 Functional Testability

? APPLICATIONS INCLUDE:

— Glue Logic for 3.3V Systems

— DMA Control

— State Machine Control

— High Speed Graphics Processing

— Standard Logic Speed Upgrade

? ELECTRONIC SIGNATURE FOR IDENTIFICATION