Family Overview

GS815018/36A are 18,874,368-bit (18Mb) high performance SRAMs. This family of wide, low voltage HSTL I/O SRAMs is designed to operate at the speeds needed to implement economical high performance cache systems.

Features

? Register-Register Late Write mode, Pipelined Read mode

? 2.5 V +200/–200 mV core power supply

? 1.5 V or 1.8 V HSTL Interface

? ZQ controlled programmable output drivers

? Dual Cycle Deselect

? Fully coherent read and write pipelines

? Byte write operation (9-bit bytes)

? Differential HSTL clock inputs, K and K

? Asynchronous output enable

? Sleep mode via ZZ

? IEEE 1149.1 JTAG-compliant Serial Boundary Scan

? JEDEC-standard 119-bump BGA package

? Pb-Free 119-bump BGA package available